ReNoC: A network-on-chip architecture with reconfigurable topology

被引：17

作者：

Stensgaard, Mikkel B. ^{[1
]}

Sparso, Jens ^{[1
]}

机构：

[1] Tech Univ Denmark, IMM, DK-2800 Lyngby, Denmark

来源：

NOCS 2008: SECOND IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/NOCS.2008.13

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a Network-on-Chip (NoC) architecture that enables the network, topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit-switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.

引用

页码：55 / 64

页数：10

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