HVIC process on bonded wafers with internal gettering

A high voltage BICDMOS process, using bonded and trench isolated wafers, was developed for internal use and foundry opportunities. Extensive use was made of the oxide isolation to achieve electrical isolation of > 1000V between elements. The Oxide isolation also allows high packing density, positive and negative voltages on the same chip, noise reduction and allows devices which inject minority carriers into the substrate. This process supports a rugged, vertical 350V DMOS, 10V CMOS, vertical NPN, lateral PNP, and a 450V SCR, together with a variety of components such as resistors, high and low voltage capacitors, Zener diodes, etc. We propose for the first time, the use of internal gettering in combination with high temperature denuding of the active layer using thermal oxidation techniques to achieve high minority carrier lifetime and enhanced gate oxide integrity (GOI). The internal gettering was achieved by the use of a pre-bond implantation and resulted in significantly enhanced minority carrier lifetime of the SOI layer.