A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC

被引：3

作者：

Di Pasquo, Alessio ^{[1
,2
]}

Nani, Claudio ^{[3
]}

Monaco, Enrico ^{[3
]}

Fanucci, Luca ^{[4
]}

机构：

[1] Univ Pisa, Pisa, Italy

[2] Inphi Pavia, Pavia, Italy

[3] Inphi, Pavia, Italy

[4] Univ Pisa, Dept Informat Engn, Pisa, Italy

来源：

2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年

关键词：

Analog-to-digital converter; Track and Hold; Buffer; Sampler;

D O I：

10.1109/ISCAS51556.2021.9401618

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior are analyzed and the key design strategies to maximize linearity are discussed. Then, a 60 GS/s, 52.6 dB SFDR, 8 ways interleaved simulated prototype in TSMC 5 nm technology, consuming 2.52 mW from a 0.9 V supply, is compared to the state-of-the-art sampling buffers, showing linearity improvement.

引用

页数：5

共 50 条

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