Electrical Characteristics of Low-Temperature Polycrystalline Silicon Complementary Metal-Oxide-Semiconductor Thin-Film Transistors with Six-Step Photomask Structure

被引:1
|
作者
Lee, Sang-Jin [1 ,2 ]
Park, Jae-Hoon [1 ]
Oh, Kum-Mi [1 ]
Lee, Seok-Woo [1 ]
Lee, Kyung-Eon [1 ]
Shin, Woo-Sup [1 ]
Jun, Myung-Chul [1 ]
Yang, Yong-Suk [3 ]
Hwang, Yong-Kee [1 ]
机构
[1] LG Display R&D Ctr, Paju 413811, Gyeonggi, South Korea
[2] Pusan Natl Univ, Dept Phys, Pusan 609735, South Korea
[3] Pusan Natl Univ, Dept Nanomat Engn, Pusan 609735, South Korea
关键词
INTERFACE STATE GENERATION; HOT-CARRIER INJECTION; LIFETIME PREDICTION; AMLCD APPLICATION; N-MOSFETS; DEGRADATION; MODEL;
D O I
10.1143/JJAP.50.061401
中图分类号
O59 [应用物理学];
学科分类号
摘要
We propose two types of six-step photomask, complementary metal-oxide-semiconductor (CMOS), thin-film transistor (TFT) PCT device structures in order to simplify their fabrication process compared with that of conventional, low-temperature, polycrystalline silicon (LTPS) CMOS TFT devices. The initial charge transfer characteristics of both types of six-step PCT are equivalent to those of the conventional nine-step PCT. Both types of six-step PCT are comparable to the conventional nine-step mask lightly doped drain (LDD) device in terms of the dc device lifetime of over 10 years at V-ds = 5 V for line inversion driving, which is the normally recognized duration time for semiconducting devices. (C) 2011 The Japan Society of Applied Physics
引用
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页数:5
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