A 3.3V transconductor in 0.35μm CMOS with 80dB SFDR up to 10MHz

被引：2

作者：

Chilakapati, U ^{[1
]}

Fiez, T ^{[1
]}

Eshraghi, A ^{[1
]}

机构：

[1] Innocomm Wireless, San Diego, CA USA

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929822

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80dB SFDR for 3.6V(pp) differential inputs up to 10MHz. The transconductance core dissipates 10.56mW from a 3.3V supply and occupies 0.4mm(2) in a 0.35 mum CMOS process.

引用

页码：459 / 462

页数：4

共 23 条

[1] A CMOS transconductor with 80-dB SFDR up to 10 MHz
Chilakapati, U
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (03) : 365 - 370
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[7] A 325 MHz 3.3V 10-bit CMOS D/A converter core with novel latching driver circuit
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[9] 1.6Gbps low-power receiver for display interfaces using a 3.3V and 0.35μm CMOS process
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[10] A 300MHz, 3.3V 1Mb SRAM fabricated in a 0.5 mu m CMOS process
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