Depleted MAPS on a 110 nm CMOS CIS Technology

A high-voltage monolithic active pixel sensor, designed to be compatible with standard deep sub-micron CMOS production lines, is described. The device can support a reverse bias voltage of -180 V and combines small collection electrodes with full wafer depletion, demonstrated up to a thickness of 300 mu m. Test structures consisting of matrices with an area of 2 mm x 2 mm embedding 576 pixels with 50 mu m pitch have been fabricated in a 110 nm CMOS process. The sensor concept is discussed and experimental measurements obtained on first prototypes are presented.