All-Digital CDR for High-Density, High-Speed I/O

被引：8

作者：

Loh, Matthew ^{[1
]}

Emami-Neyestanak, Azita ^{[1
]}

机构：

[1] CALTECH, Pasadena, CA 91125 USA

来源：

2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2010年

关键词：

CDR; static CMOS; all-digital;

D O I：

10.1109/VLSIC.2010.5560319

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel all-digital CDR for source-synchronous links, and its implementation in 90nm CMOS, is presented. A phase alignment technique with ping-pong action between two clock phases is used. The system is implemented in static CMOS logic, occupies 0.234 mm(2) and dissipates 16.6 mW at 6 Gb/s, demonstrating BER < 10(-13) with PRBS-7 input. The compactness and all-static-CMOS nature of the system make it suitable for use in high-speed I/Os requiring per-pin synchronization.

引用

页码：147 / 148

页数：2

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