Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors

被引：14

作者：

Manzini, S ^{[1
]}

Gallerano, A ^{[1
]}

Contiero, C ^{[1
]}

机构：

[1] SGS Thomson Microelect, Dedicated Prod Grp, I-20010 Milano, Italy

来源：

ISPSD '98 - PROCEEDINGS OF THE 10TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS | 1998年

关键词：

D O I：

10.1109/ISPSD.1998.702734

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The basic parameter controlling the hot-electron safe operating area of DMOS transistors integrable in submicron Bipolar-CMOS-DMOS mixed processes is the series resistance of the n-type lightly-doped layer on the source side of the devices. The hot-electron-induced degradation in DMOS transistors is correlated with the hot-electron gate current -rather than with the substrate (p-body) current- and its measurement is a sensitive, nondestructive way to bypass long-term reliability tests.

引用

页码：415 / 418

页数：4

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