A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS

被引：34

作者：

Darabiha, Ahmad ^{[1
]}

Carusone, Anthony Chan ^{[1
]}

Kschischang, Frank R. ^{[1
]}

机构：

[1] Univ Toronto, Dept Elect & Comp Engn, Toronto, ON, Canada

来源：

PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2007年

关键词：

D O I：

10.1109/CICC.2007.4405773

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-mu m CMOS prototype. It occupies 7.3-mm(2) core area with 1416-mW maximum power consumption from a 1.2-V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.

引用

页码：459 / 462

页数：4

共 3 条

[1] A bit-serial approximate min-sum LDPC decoder and FPGA implementation
Darabiha, Ahmad
Carusone, Anthony Chan
Kschischang, Frank R.
[J]. 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 149 - +
[2] 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code
Hemati, S
Banihashemi, AH
Plett, C
[J]. CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, : 243 - 246
[3] A 0.18-μm CMOS analog min-sum iterative decoder for a (32,8) low-density parity-check (LDPC) code
Hemati, Saied
Banihashemi, Amir H.
Plett, Calvin
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (11) : 2531 - 2540

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