Quality Assurance Verification using a Virtual Prototyping System

被引：0

作者：

McGarry, L ^{[1
]}

Qu, KY ^{[1
]}

Lee, W ^{[1
]}

Sun, M ^{[1
]}

Wilson, TG ^{[1
]}

机构：

[1] Astec Custom Power HK Ltd, Kowloon, Hong Kong, Peoples R China

来源：

APEC 2005: TWENTIETH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, VOLS 1-3 | 2005年

关键词：

Quality Assurance Verification; Virtual Prototyping; electronic Design Verification Test (eDVT); Intellectual Property (IP) Blocks; SIMPLIS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

concept of a Virtual Prototyping System using simulation and IP Blocks has been previously outlined in [1]. This paper discusses an extension of the virtual prototyping simulation system by applying those tools and techniques to simulate many of the parameters required to complete a Quality Assurance Verification (QAV) Test. These include electrical parameter stress, worst case analysis, component de-rating, worst case system over stress and impact on MTBF calculations.

引用

页码：1325 / 1331

页数：7

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