DESIGN OF ENERGY EFFICIENT SEMI-SERIAL ON-CHIP COMMUNICATION LINK

被引：0

作者：

Priyadharsini, R. Ranga ^{[1
]}

Paramasivam, K. ^{[1
]}

机构：

[1] Karpagam Coll Engn, DEPT ECE, Coimbatore, Tamil Nadu, India

来源：

PROCEEDINGS OF 2015 ONLINE INTERNATIONAL CONFERENCE ON GREEN ENGINEERING AND TECHNOLOGIES (IC-GET) | 2015年

关键词：

Network on-chip; Differential pulse current-mode signaling; Pulse signaling; Wave pipelining;

D O I：

暂无

中图分类号：

X [环境科学、安全科学];

学科分类号：

08 ; 0830 ;

摘要：

Low energy semi-serial on-chip communication link is to be designed. This link is designed using high speed serialization/deserialization and pulse dual rail encoding techniques. The link also consists of wave-pipelined differential pulse current-mode signaling to maintain the high speed data intake from the serializer. The energy efficiency of the proposed semi-serial link, which consists of bit serial links in parallel, mainly comes from sharing of serializer's control circuit among the bit-serial links. In addition, the integration of pulse signaling with wave-pipelining, the use of a new low-complexity data validity detection technique, and the avoidance of data decoding logic also contribute to power reduction.

引用

页数：6

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