A VLSI Design of Sensor Node for Wireless Image Sensor Network

This paper presents a single chip VLSI architecture of wireless image sensor node, which is constituted by an enhanced embedded 8051 microcontroller, a CMOS camera interface and hardware accelerators. The algorithms and control flows of the IEEE 802.15.4 MAC layer are accelerated by hardware, results in 45% less code size compared with the conventional software stack. An innovated CFA preprocessing algorithm and JPEG-LS compressing method is adopted and implemented by hardware, which has a minimal 46.3dB PSNR, an average compression ratio of about 3.0bit/pixel and an approximately 5fps at 16MHz system clock. Furthermore, low power design and techniques are employed to extend battery life, resulting in 60mW max system power consumption when the SoC is in full working mode (i.e. processor, image processing and wireless communication are active simultaneously) in 0.18 mu m CMOS process.