Side Channel Attack Resistant Architecture for Elliptic Curve Cryptography

With the widespread use of applications like internet banking, secured communication, emails, etc. information security is important concern. Security of information depends on implementation of cryptographic algorithm and its complexity to solve in reverse direction. However, with the use of current high speed computational resources it is possible to carry out brute-force attack and various other techniques like analyzing power, temperature, timing information. Therefore, cryptosystems are always under the threat of attacks. Elliptic Curve Cryptography is system based on the theory of elliptic curves. It is very promising technique as it offers better security with shorter key length compared to other contemporary techniques of encryption like AES, RSA etc. It is widely accepted that 160-bit ECC offers equivalent security as of 1024-bit RSA. This feature makes ECC attractive for constrained based devices where less power and storage and computing is required. FPGAs are suitable platform for implementing the cryptosystem as they provides rapid prototyping. However, hardware implementation of crypto algorithm can leak secret information through side channel attacks considerably weakens the system security. Typically, power consumption, timing information, electromagnetic information or inserting faults adversary can analyze the system. The proposed work focuses on to avoid the attacker from gaining the secret information from the system. This is done inserting noise, redundant computations or by false random traces and with focus on tradeoff of VLSI design i. e. Power, Area and Delay.