Energy-efficient H.264 video decoding on VLIW embedded processors

被引：0
|
作者：
Hu, Y [1 ]
Li, Q [1 ]
Kuo, CCJ [1 ]
机构：
[1] Univ So Calif, Integrated Media Syst Ctr, Los Angeles, CA USA
来源：
EMBEDDED PROCESSORS FOR MULTIMEDIA AND COMMUNICATIONS II | 2005年 / 5683卷
关键词：
VLIW; embedded processor; energy optimization; H.264;
D O I：
10.1117/12.589673
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The energy consumption profiling of the H.264 video decoder on VLIW embedded processors using the Trimaran simulator is conducted. Based on this study, we observe that the branch operations in the quarter-pixel (QP) interpolation and the DCT slow down the issue rate of the VLIW processors. Then, several new instruction architecture sets are proposed to address this issue. These new instructions can be used to speedup the issue rate, and reduce the total energy consumption. Finally, experimental results of the proposed instruction-level power-efficient strategies on the TI C6416 processor are reported and discussed.
引用
收藏
页码：9 / 20
页数：12
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