On Flip-Flop Selection for Multi-Cycle Scan Test with Partial Observation in Logic BIST

Multi-cycle test with partial observation for scan-based logic BIST is known as one of effective methods to improve fault coverage without increase of test time. In the method, the selection of flip-flops for partial observation is critical to achieve high fault coverage with small area overhead. This paper proposes a selection method under the limitation to a number of flip-flops. The method consists of structural analysis of CUT and logic simulation of test vectors, therefore, it provides an easy implementation and a good scalability. Experimental results on benchmark circuits show that the method obtains higher fault coverage with less area overhead than the original method. Also the relation between the number of selected flip-flops and fault coverage is investigated.