Low-voltage and low-power adjustable differential delay line using the FGMOS transistor

This paper proposes a novel low-voltage and low-power analog differential delay line CMOS circuit design in the audio frequency range. The circuit is based on the G.-C linear integrator used as the main block in a low-pass filter which can be tuned varying a bias voltage. To overcome the dynamic range problems by the supply voltage reduction, the design is implemented using the FGMOS transistor. The simulated results in a 1.2 mu m CMOS technology show that delay time can be adjustable through 6 tap with a dissipation power of 140 mu W and a supply voltage of 1.5V.