共 50 条
- [31] An efficient test relaxation technique for combinational circuits based on critical path tracing [J]. ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 461 - 465
- [33] A Research of Heuristic Optimization Approaches to the Test Set Compaction Procedure Based On aDecomposition Tree for Combinational Circuits [J]. PROCEEDINGS OF IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2013), 2013,
- [35] State relaxation based subsequence removal for fast static compaction in sequential circuits [J]. DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 577 - 582
- [37] Vector restoration based static compaction of test sequences for synchronous sequential circuits [J]. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, : 360 - 365
- [39] Class-based models in the π-calculus [J]. TECHNOLOGY OF OBJECT-ORIENTED LANGUAGES AND SYSTEMS (TOOLS 25) - PROCEEDINGS, 1998, : 238 - 251
- [40] SYNTHESIS OF COMBINATIONAL SWITCHING-CIRCUITS CONTAINING NO STATIC HAZARDS [J]. AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1979, (03): : 1 - 6