Reconfigurable Embedded System Architecture for Next-Generation Neural Signal Processing

被引：6

作者：

Balasubramanian, Karthikeyan ^{[1
]}

Obeid, Iyad ^{[1
]}

机构：

[1] Temple Univ, Neural Instrumentat Lab, Philadelphia, PA 19122 USA

来源：

2010 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC) | 2010年

关键词：

ALGORITHMS;

D O I：

10.1109/IEMBS.2010.5626833

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

This work presents a new architectural framework for next generation Neural Signal Processing (NSP). The essential features of the NSP hardware platform include scalability, reconfigurability, real-time processing ability and data storage. This proposed framework has been implemented in a proof-of-concept NSP prototype using an embedded system architecture synthesized in a Xilinx (R) Virtex (R) 5 development board. The prototype includes a threshold-based spike detector and a fuzzy logic-based spike sorter.

引用

页码：1691 / 1694

页数：4

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