Dynamic voltage scheduling using adaptive filtering of workload traces

被引：24

作者：

Sinha, A ^{[1
]}

Chandrakasan, AP ^{[1
]}

机构：

[1] MIT, Dept EECS, Cambridge, MA 02139 USA

来源：

VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN | 2001年

关键词：

D O I：

10.1109/ICVD.2001.902664

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An adaptive approach for dynamic voltage scheduling on processors is presented based on workload prediction by filtering a trace history. The effects of update frequency and filtering strategy on the energy savings is analyzed. A performance hit metric is defined and techniques to minimize energy under a given performance requirement are outlined. Our results demonstrate that up to two orders of magnitude energy savings is possible with dynamic voltage scheduling depending on workload statistics.

引用

页码：221 / 226

页数：6

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