Improving path delay fault testability by path removal

被引：2

作者：

Sparmann, U ^{[1
]}

Koller, L ^{[1
]}

机构：

[1] Univ Saarland, Dept Comp Sci, D-66123 Saarbrucken, Germany

来源：

16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/VTEST.1998.670869

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

It has been shown previously, that paths which are internally fanout free and not non-robustly testable with respect to at least one transition? can be removed from a circuit without changing its functional behavior. This transformation has been successfully applied in order to remove long false paths from a given circuit. In this work, we show how to apply the above transformation in order to improve delay testability. Experimental results demonstrate that large improvements in testability can be obtained at low hardware costs. In addition, the delay of the circuits is even reduced in most cases.

引用

页码：200 / 208

页数：9

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