An Analysis Technique for Improving Delay Factor of Carry Select Adder using FPGA

New delay-efficient configurable multiplier based on Modified Booth's Algorithm (MBA) and Wallace Tree (WT) structure for multiplying two m-bit operands- where in ranges from 8-bit to 128-bit is introduced. WT structure has been used to reduce the number of sequential adding stages and speed improvements have been achieved. Modifying Booth's multiplier architecture at a fundamental level is an advantageous concept that sets FPGA based multiplier models apart from rigid architecture conventional multipliers. In the context of this work, various multipliers, based on MBA and WT, have been developed with the smallest possible time delay. Comparisons have been made between the proposed multiplier implementations and those found in the literature. The comparative results show that the proposed multiplier introduces delay improvement reaches % 42.64.