A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement

被引：2

作者：

Kim, Tae-Ho ^{[1
]}

Moon, Yong-Hwan ^{[1
]}

Kang, Jin-Ku ^{[1
]}

机构：

[1] Inha Univ, Sch Elect Engn, Inchon 402751, South Korea

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2011年 / E94C卷 / 11期

基金：

新加坡国家研究基金会;

关键词：

adaptive algorithm; feed-forward equalizer (FFE); decision-feedback equalizer (DFE); data-dependent jitter (DDJ); 0.13-MU-M CMOS; EQUALIZER; CLOCK;

D O I：

10.1587/transele.E94.C.1779

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an adaptive FFE/DFE receiver with an algorithm that measures the data-dependent jitter. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a clock and data recovery phase detector. The receiver is fabricated in with 0.13 mu m CMOS technology, and the compensation range of equalization is up to 26 dB at 2 GHz. The test chip is verified for a 40 inch FR4 trace and a 53 cm flexible printed circuit channel. The receiver occupies an area of 440 mu m x 520 mu m and has a power dissipation of 49 mW (excluding the I/O buffers) from a 1.2 V supply.

引用

页码：1779 / 1786

页数：8

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