A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS

Y A 32-Gb/s adaptive receiver analog front-end (AFE) with a hybrid continuous-time linear equalizer (CTLE), a half-rate distributed edge and data decision feedback equalizer (DFE) and a clock data recovery (CDR) is presented. The hybrid CTLE counters the low-frequency as well as the high-frequency loss of 21 dB at Nyquist. Further post-cursors can be solved by using a half- rate, distributed 3-tap edge-DFE and 2-tap data-DFE, which is partially embedded in the CDR. The distributed DFE scheme addresses the inter symbol interference (ISI) at the edge and reduces the data jitter while data-DFE guarantees the vertical opening of the data eye. Fabricated in 65-nm CMOS, occupying an active area of 0.3 mm(2), the proposed prototype demonstrates an improvement of 0.15 UI in the horizontal eye opening of the data output at a receiver AFE with the conventional 5-tap data-DFE at BER=10(-12,) under a pseudorandom binary sequence (PRBS) of 2(31)-1. The competitive power efficiency of 3.53 mW/Gb/s is measured with a supply voltage of 1.2 V.