Periodic real-time scheduling for FPGA computers

Todays reconfigurable hardware devices, such as FPGAs, have high densities and allow for the execution of several hardware tasks in parallel. This paper deals with scheduling periodic real-time tasks to such an architecture, a problem which has not been considered before. We formalize the real-time scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known Earliest Deadline First (EDF) technique to the FPGA execution model. The algorithm reveals good scheduling performance; task sets with system utilizations of up to 85% can be feasibly scheduled. However the EDF approach is practical only for a small number of tasks, since there is no efficient schedulability test. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method can only feasibly schedule task sets with a system utilization of up to some 50%, it is applicable to large tasks sets as the schedulability test runs in polynomial time. Equally important, the method requires only a small number of FPGA configurations which directly translates into reduced memory requirements.