Design of a soft error hardened SRAM cell with improved access time for embedded systems

Recent advancements in high-performance processor operation have nurtured the requirement of low power, reliable, and fast static random-access memory (SRAM). Scaling supply voltage is the most preferred technique while minimizing the power dissipation in SRAM cells. However, several challenges follow with this improvement including, increased soft errors and diminishing operating speed. A novel 12T SRAM cell is presented in this work for improving critical charge and operating speed. The improvement in key parameters of the proposed cell is affirmed by comparing with recently reported circuits that use various improvement techniques, i.e., standard 6T (S6T), tunable access transistors 8T (T8T), PPN based 10T (PP10T), Schmitt-trigger based 10T (ST10T), Soft error hardened 10T (SEH10T), Schmitt trigger based 11T (ST11T), stable low power 11T (SL11T), and data-dependent 11T (DPS11T) cell. The critical charge of the proposed 12T is improved by 1.39x/1.30x/1.69x/0.79x/0.92x//1.51x/1.02x/1.6 2x comparing with S6T/T8T/PP10T/ST10T/SEH10T/ST11T/SL11T/DPS11T SRAM cell. Moreover, the proposed cell successfully mitigates the half-select issue that allows implementing a bit-interleaved array. The access time in proposed 12T during read and write operations is reduced by 1.14x/1.04x/1.11 x/1.11 x/1 x/1.02x/1.12x/1.01 x and 0.97x/1.02x/1.70x/0.96x/1.39x/0.99x/0.93x/0.96x respectively comparing with S6T/T8T/PP10T/ST10T/ SEH10T/ST11T/SL11T/DPS11T SRAM cell. The enhancement in read stability and write ability of the proposed 12T is represented by 1.21x/1.09x/0.60x/0.88x/0.61x/0.61x/1.08x/1.10x and 1.06x/1.10x/1.29x/0.82x/ 0.93x/1.06x/0.80x/1.05x variation in read and write static noise margin, respectively comparing with S6T/T8T/PP10T/ST10T/SEH10T/ST11T/SL11T/DPS11T cell. Also, the proposed 12T require low data retention voltage in contrast to other considered cells.