Worst-Case Test Vectors of FPGAs Exposed to Total Dose

被引：0

作者：

Abou-Auf, Ahmed A. ^{[1
]}

Abdel-Aziz, Mostafa M. ^{[1
]}

Elkady, Mai A. ^{[1
]}

Ammar, Adel A. ^{[1
]}

机构：

[1] Amer Univ Cairo, Elect Engn Dept, AUC Ave,POB 74, New Cairo 11835, Egypt

来源：

2016 16TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We introduce a novel methodology for identifying the worst-case test vector for flash-based FPGA devices exposed to total ionizing dose based on cell-level fault models of delay failures.

引用

页数：4

共 50 条

[1] Fault Modeling and Worst-Case Test Vectors of Sequential ASICs Exposed to Total Dose
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[2] Worst Case Test Vectors for Sequential Circuits in Flash-Based FPGAs Exposed to Total Dose
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[3] Fault Modeling and Worst-Case Test Vectors for Delay Failures Induced by Total Dose in ASICs
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[4] Fault Modeling and Worst-Case Test Vectors for Leakage Current Failures Induced by Total Dose in ASICs
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[5] Worst-case test vectors for functional failure induced by total dose in CMOS microcircuits with transmission gates
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[6] Worst-case test vectors for functional failure induced by total dose in CMOS microcircuits with transmission gates
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[7] Fault Modeling and Worst Case Test Vector Generation for Flash-Based FPGAs Exposed to Total Dose
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[8] A METHODOLOGY FOR THE IDENTIFICATION OF WORST-CASE TEST VECTORS FOR LOGICAL FAULTS INDUCED IN CMOS CIRCUITS BY TOTAL-DOSE
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[10] Gate-level modeling of leakage current failure induced by total dose for the generation of worst-case test vectors
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