An Approach: SysML-based Automated Requirements Verification

Systems Modeling Language (SysML) is used to capture systems design as descriptive and analytical system models, which relate text-based requirements to the system design model and provide an infrastructure to support analysis and verification. However, SysML is not a methodology, nor a method. This opens-up discussions of how to utilize SysML provided infrastructure to successfully achieve analysis and verification objectives in the context of a particular engineering problem. In this paper a new approach of how model of the system, expressed with sufficient precision in SysML, can be used to support early requirements validation and design verification, particularly when coupled with standard-based execution and simulation environment, is introduced.