A Novel 3-D Space Vector Modulation Algorithm for Cascaded Multilevel Inverter

Multilevel inverters have been widely used in high-power applications, because of its low switching losses and good harmonic rejection capabilities. Various multilevel pulse width modulation (PWM) strategies have been developed. Among them, space-vector pulse width modulation (SVPWM) technique offers significant flexibility to optimize switching waveforms and is well suited for digital implementation. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm for n-level three-phase inverters. The 3-D SVPWM presented in this paper can be applied practically in hybrid multilevel inverters with unequal or varying voltage steps; it can be applied to most multilevel topologies. The algorithm offers an intuitive method for minimizing the total harmonic distortion (THD) of the output voltage of the inverter and the proposed techniques lead to a significant reduction in THD. The algorithm developed improves factor such as the computational cost and voltage distortion. Finally, the algorithm was implemented on a Field programmable gate array (FPGA) and the scheme is explained for a five level inverter, and experimental results are presented for single phase five-level cascaded inverter to validate the proposed modulation technique. Copyright (C) 2011 Praise Worthy Prize S.r.l. - All rights reserved.