Test structures for the characterization of MEMS and CMOS integration technology

被引：3

作者：

Lin, Huamao ^{[1
]}

Walton, Anthony J. ^{[1
]}

Dunare, Camelia C. ^{[1
]}

Stevenson, J. Tom M. ^{[1
]}

Gundlach, Alan M. ^{[1
]}

Smith, Stewart ^{[1
]}

Bunting, Andrew S. ^{[1
]}

机构：

[1] Univ Edinburgh, Inst Integrated Micro & Nano Syst, Sch Engn & Elect, Scottish Microelect Ctr, Edinburgh EH9 3JF, Midlothian, Scotland

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 2008年 / 21卷 / 02期

关键词：

chemical-mechanical polishing (CMP); complementary metal-oxide semiconductor(CMOS)-microelectromechanical systems (MEMS) integration; IC interconnections; Kelvin test structure; low-temperature wafer direct bonding; metallization plasma activation;

D O I：

10.1109/TSM.2008.2000274

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical-mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8-5.2 Omega have been obtained from via chain test structures and an average specific contact resistivity of 1.7 x 10(-8) Omega cm(2), measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.

引用

页码：140 / 147

页数：8

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