共 50 条
- [21] A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2016, 32 (05): : 611 - 624
- [22] On the Need of Randomness in Fault Attack Countermeasures - Application to AES 2012 WORKSHOP ON FAULT DIAGNOSIS AND TOLERANCE IN CRYPTOGRAPHY (FDTC), 2012, : 85 - 94
- [23] A Biased Fault Attack on the Time Redundancy Countermeasure for AES CONSTRUCTIVE SIDE-CHANNEL ANALYSIS AND SECURE DESIGN, COSADE 2015, 2015, 9064 : 189 - 203
- [24] Fault Sensitivity Analysis Meets Zero-Value Attack 2014 WORKSHOP ON FAULT DIAGNOSIS AND TOLERANCE IN CRYPTOGRAPHY (FDTC 2014), 2014, : 59 - 67
- [25] Differential Fault Analysis Against AES Based on a Hybrid Fault Model NEURAL INFORMATION PROCESSING, ICONIP 2023, PT IV, 2024, 14450 : 161 - 171
- [26] Cache based AES attack implementation and its theoretical analysis Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2011, 48 (06): : 955 - 963
- [27] Template Attack Against AES in Counter Mode With Unknown Initial Counter 2023 IEEE 13TH ANNUAL COMPUTING AND COMMUNICATION WORKSHOP AND CONFERENCE, CCWC, 2023, : 525 - 533
- [28] Key Advantage Template Attack Against AES-128 Algorithm Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2020, 48 (10): : 2003 - 2008
- [30] Glitch-Resistant Masking Schemes as Countermeasure Against Fault Sensitivity Analysis 2018 WORKSHOP ON FAULT DIAGNOSIS AND TOLERANCE IN CRYPTOGRAPHY (FDTC), 2018, : 27 - 34