Improvement of high-voltage junction termination extension (JTE) by an optimized profile of lateral doping (VLD)

被引：6
|
作者：
Ronsisvalle, C. [1 ]
Enea, V. [1 ]
机构：
[1] STMicroelectronics, IMS R&D, I-95127 Catania, Italy
来源：
MICROELECTRONICS RELIABILITY | 2010年 / 50卷 / 9-11期
关键词：
D O I：
10.1016/j.microrel.2010.07.078
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The planar edge termination technique of junction termination extension (JTE) was investigated and optimized by using a two-dimensional device simulator. Particular attention was paid to achieve the least electrical field at the silicon/oxide interface of JTE region in order to decrease the surface charges sensitivity and then the reliability of the structure. (C) 2010 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1773 / 1777
页数：5
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