High-throughput, area-efficient hardware architecture of CABAC-Binarization for UHD applications

Video compression imposes a high throughput requirement on the latest video encoders (HEVC and VVC), and CABAC is primarily used entropy method in such applications. Binarization is first and vital sub-block of CABAC that requires high throughput and better performance. A high-throughput and area-efficient Binarization has been proposed in this work. A parallel processing hardware architecture is used, which processes five input symbols per clock cycle and probability estimation to obtain high throughput. The resource sharing technique is used to optimize the utilization of hardware resources. Further, a pairing-SEs scheme and storage buffers have been incorporated in the data path for better performance. The Binarization architecture is designed in Verilog HDL and verified on Artix-7 FPGA. It is also implemented on ASIC using 90 nm technology. The proposed design achieved a maximum throughput of 3.14 Gbin/s at 282 MHz and consumed considerably low hardware area as compared to other architectures. The proposed Binarization is adaptive, scalable, and versatile in functionality.