FPGA supported rough set reduct calculation for big datasets

The rough sets theory developed by Prof. Z. Pawlak is one of the tools used in intelligent systems for data analysis and processing. In modern systems, the amount of the collected data is increasing quickly, so the computation speed becomes the critical factor. One of the solutions to this problem is data reduction. Removing the redundancy in the rough sets can be achieved with the reduct. Most of the algorithms for reduct generation are only software implementations, resulting in many limitations coming from using the fixed word length, as well as consuming the time for fetching and processing of the instructions and data. These limitations make the software-based implementations relatively slow. Unlike software-based systems, hardware systems can process data much faster. This paper presents FPGA and softcore CPU based device for large datasets reduct calculation using rough set methods. Presented architecture has been tested on two real datasets by downloading and running presented solutions inside FPGA. Tested datasets had 1 000 to 1 000 000 objects. For the research purpose, the algorithm was also implemented in C language and ran on a PC. The time of a reduct calculation in hardware and software was considered. The obtained results show an increase in the speed of data processing.