In2O3 Nanowire Field-Effect Transistors with Sub-60 mV/dec Subthreshold Swing Stemming from Negative Capacitance and Their Logic Applications

被引:36
|
作者
Xu, Qian [1 ,2 ]
Liu, Xingqiang [1 ,3 ]
Wan, Bensong [1 ]
Yang, Zheng [1 ,2 ]
Li, Fangtao [1 ]
Lu, Junfeng [1 ]
Hu, Guofeng [1 ]
Pan, Caofeng [1 ,2 ,4 ]
Wang, Zhong Lin [1 ,2 ,5 ]
机构
[1] Chinese Acad Sci, CAS Ctr Excellence Nanosci, Beijing Inst Nanoenergy & Nanosyst, Beijing Key Lab Micronano Energy & Sensor, Beijing 100083, Peoples R China
[2] Univ Chinese Acad Sci, Sch Nanosci & Technol, Beijing 100049, Peoples R China
[3] Hunan Univ, Sch Phys & Elect, Changsha 410082, Hunan, Peoples R China
[4] Guangxi Univ, Ctr Nanoenergy Res, Sch Phys Sci & Technol, Nanning 530004, Guangxi, Peoples R China
[5] Georgia Inst Technol, Sch Mat Sci & Engn, Atlanta, GA 30332 USA
基金
中国国家自然科学基金; 北京市自然科学基金;
关键词
field-effect transistors; subthreshold swing; negative capacitance; In2O3; logic circuit; POLYMER MEMORY; PERFORMANCE; DRIVEN; DEVICE;
D O I
10.1021/acsnano.8b05604
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
Heat dissipation is a key issue for scaling metal-oxide-semiconductor field-effect transistors (MOSFETs). The Boltzmann distribution of electrons imposes a physical limit on the subthreshold swing (SS), which impedes both the reduction of the switching energy and the further increase of the device density. The negative capacitance effect is proposed to rescue MOSFETs from this phenomenon called "Boltzmann tyranny". Herein, we report In2O3 nanowire (NW) transistors with SS values in the sub-60 mV/dec region, which utilize the ferroelectric P(VDF-TrFE) as the dielectric layer. An ultralow SS down to similar to 10 mV/dec is observed and spans over 5 orders of magnitude in the drain current. Meanwhile, a high on/off ratio of more than 10(8) and a transconductance (g(m)) of 2.3 mu S are obtained simultaneously at V-d = 0.1 V. The results can be understood by the "voltage amplification" effect induced from the negative capacitance effect. Moreover, the steep slope FET-based inverters indicate a high voltage gain of 41.6. In addition to the NOR and NAND gates, the Schmitt trigger inverters containing only one steep slope FET are demonstrated. This work demonstrates an avenue for low-power circuit design with a steep SS.
引用
收藏
页码:9608 / 9616
页数:9
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