共 50 条
- [1] A Novel BIST Approach for Testing DLLs of SoC IEEE CIRCUITS AND SYSTEMS INTERNATIONAL CONFERENCE ON TESTING AND DIAGNOSIS, 2009, : 360 - 363
- [2] Integrating BIST techniques for on-line SoC testing 11TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, 2005, : 235 - 240
- [3] A hybrid BIST architecture and its optimization for SoC testing PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2002, : 273 - 279
- [4] BIST Architecture for Multiple RAMs in SoC 7TH INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING & COMMUNICATIONS (ICACC-2017), 2017, 115 : 159 - 165
- [5] Experimental Results of Testing a BIST ε-Δ ADC on the HOY Wireless Test Platform JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2012, 28 (05): : 571 - 584
- [6] Experimental Results of Testing a BIST Σ–Δ ADC on the HOY Wireless Test Platform Journal of Electronic Testing, 2012, 28 : 571 - 584
- [7] Keyed Logic BIST for Trojan Detection in SoC 2014 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC), 2014,
- [8] Configuration free SOC interconnect BIST methodology Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an, 2001, 8 (04): : 377 - 386
- [9] Collaborative Verification and Testing Platform for NoC-based SoC WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE, WCECS 2015, VOL I, 2015, : 49 - 54
- [10] Testing based SoC/VLSI IP identification and protection platform 2007 IEEE INSTRUMENTATION & MEASUREMENT TECHNOLOGY CONFERENCE, VOLS 1-5, 2007, : 651 - +