Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies

被引：3

作者：

Chiang, Hung-Li ^{[1
]}

Wu, Jui-Jen ^{[1
]}

Chou, Chen-Han ^{[2
]}

Hsiao, Yen-Fu ^{[2
]}

Chen, Yi-Chun ^{[2
]}

Liu, Leo ^{[1
]}

Wang, Jer-Fu ^{[1
]}

Chen, Tzu-Chiang ^{[1
]}

Liao, Pei-Jun ^{[2
]}

Cai, Jin ^{[2
]}

Bao, Xinyu ^{[1
]}

Cheng, Alan ^{[2
]}

Chang, Meng-Fan ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co, Corp Res, Hsinchu, Taiwan

[2] Taiwan Semicond Mfg Co, Hsinchu, Taiwan

来源：

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2021年

关键词：

D O I：

10.1109/IEDM19574.2021.9720573

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Cold CMOS (CMOS circuits operated at 77K, usually obtained by liquid cooling system) is a feasible technology to obtain high performance computing (HPC) or power reduction by offering a reliable way for a steeper subthreshold slope (SS). Other benefits including higher mobility, metal lines with lower resistance, and enhanced reliability also provide opportunities to redesign the architecture for Cold CMOS. In this paper, we focus on DTCO (design-technology co-optimization) and PPA (power-performance-area) analyses for memory cells and their peripherals to maximize the PPA benefits from Cold CMOS at the system level.

引用

页数：4

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