Hexagonal Tiling based Multiple FPGAs Stencil Computation Acceleration and Optimization Methodology

Nowadays, multiple Field Programmable Gate Arrays (FPGAs) accelerators have been widely used in stencil computation fields. However, the state-of-the-art hexagonal tiling algorithm that efficiently improves stencil computation performance is mainly designed for CPUs or GPUs, which not suitable to directly process on FPGAs, leading to lower performance. To address this, a hexagonal tiling based multiple FPGAs stencil computation architecture and the corresponding optimization algorithm are proposed in this paper. The architecture uses the on-chip registers to store and carry cells data of a hexagonal tile. In this way, the scale and size of tiles are dramatically increased as well as the intra-FPGA calculation performance. Then, to take full advantage of multiple FPGAs processing ability, a memory shared inter-FPGAs high speed data transfer structure is devised. Finally, the Mixed-Integer Linear Programming (MILP) is used to optimize an objective function which considers the candidate FPGAs costs, computation latency and resources utilization to obtain a desirable tile size and layout result. The proposed method has been validated on the FPGA cluster which consists of two Xilinx Alveo U50 and one Alveo U250 devices. And experimental results show that we achieve performance up to 580 Gflop/s using one U50 device and 2261 Gflop/s using three FPGAs. The proposed optimizer is also tested with state-of-the-art multiple FPGAs stencil computation acceleration method and the performance is increased by 21.8% at most and 20.04% on average.