A sub-mW MPEG-4 motion estimation processor core for mobile video application

被引：5
|
作者：
Miyakoshi, J [1 ]
Kuroda, Y [1 ]
Miyama, M [1 ]
Imamura, K [1 ]
Hashimoto, H [1 ]
Yoshimoto, M [1 ]
机构：
[1] Kanazawa Univ, Fac Engn, Kanazawa, Ishikawa 9208667, Japan
来源：
PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年
关键词：
D O I：
10.1109/CICC.2003.1249386
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a Gradient Descent Search algorithm combined with a Sub Block search method that reduces required computation power to 8 MOPS maintaining high picture quality as equivalent as a Full Search method, and an optimized SIMD datapath. architecture to decrease a clock frequency and an operating voltage. It has been designed with CMOS 5-metal 0.18 um rule. The estimated power consumption to process a QCIF 15 fps video is less than 1 mW at 1.70 MHz@1.0 V.
引用
收藏
页码：181 / 184
页数：4
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