2 Gbit/s transimpedance amplifier fabricated by 0.35 μm CMOS technologies

被引：12

作者：

Kuo, CW ^{[1
]}

Hsiao, CC ^{[1
]}

Yang, SC ^{[1
]}

Chan, YJ ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Chungli 32054, Taiwan

来源：

ELECTRONICS LETTERS | 2001年 / 37卷 / 19期

关键词：

D O I：

10.1049/el:20010797

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Integrated CMOS transimpedance, (TZ) amplifier circuits have been designed and fabricated based on a home-made BSIM model. A 0.35 mum CMOS technology was used for circuit realisation, and a capacitive-peaking design to improve the bandwidth of the TZ amplifier is proposed and investigated. Using this approach provides an easy way to improve the performance of the TZ amplifier; the measured 3 dB bandwidth is enhanced from 875 MHz to 1.35 GHz. The CMOS TZ amplifier design achieves a 2 Gbit/s data rate.

引用

页码：1158 / 1160

页数：3

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