Reduction of test vectors volume by means of gate-level reconfiguration

被引：0

作者：

Starecek, Lukas ^{[1
]}

Sekanina, Lukas ^{[1
]}

Kotasek, Zdenek ^{[1
]}

机构：

[1] Brno Univ Technol, Fac Informat Technol, Brno 61266, Czech Republic

来源：

2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.

引用

页码：255 / 258

页数：4

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