MPEG-4 video encoder based on DSP-FPGA techniques

With the development of video encoding techniques, video compression algorithms become more complicated. A real-time high resolution video encoder cannot be implemented with a single CPU or DSP. We design and implement a MPEG-4 video encoder based on coordinated DSP-FPGA techniques. The FPGA module takes the tasks of video acquisition, YUV separation and data I/O functions, while the DSP is dedicated for video compression. We optimize data flow scheme of the MPEG-4 video compression to utilize the DSP's on-chip memory. A MB (Macro Block) type judging algorithm is proposed based on MB's space complexity. It effectively reduces the computational complexity of the video compression The experimental results indicate that our MPEG-4 video encoder implementation can encode 39.2 fps in CIF resolution.