A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM

被引：0
|
作者：
Beshay, Peter [1 ]
Calhoun, Benton H. [1 ]
Chandra, Vikas [2 ]
Aitken, Rob [2 ]
机构：
[1] Univ Virginia, Charlottesville, VA 22904 USA
[2] ARM Inc, San Jose, CA USA
来源：
PROCEEDINGS OF THE 2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) | 2014年
关键词：
Low power SRAM; Adaptive Stability; Calibration; Dynamic Margin Sensor; Wordline Quantization; Wordline Control;
D O I：
10.1145/2627369.2627662
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The conventional guard band design approach increases the SRAM Wordline (WL) pulse duration to operate successfully in all the process, voltage and temperature (PVT) corners. This can significantly increase the dynamic energy. This work presents a digital circuit that is able to track and control the WL pulse duration of the SRAM memory across PVT variations, to minimize the dynamic energy while maintaining robust operations. The circuit is applied on a 78kbit SRAM. The results are compared to the worst case margin approach and show a maximum write energy savings of 45% and 49% relative to margining voltage/temperature (VT) and process variations, respectively.
引用
收藏
页码：307 / 310
页数：4
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