Fabrication of 0.1μm-gate InPHEMTs using i-line lithography

被引：0

作者：

Sawada, K ^{[1
]}

Makiyama, K ^{[1
]}

Takahashi, T ^{[1
]}

Nozaki, K ^{[1
]}

Igarashi, M ^{[1
]}

Kon, J ^{[1
]}

Hara, N ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, Atsugi, Kanagawa 2430197, Japan

来源：

2003 INTERNATIONAL CONFERENCE INDIUM PHOSPHIDE AND RELATED MATERIALS, CONFERENCE PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We developed a new process (PATRASH: PAttern TRAnsfer SHrink) for fabricating T-shaped 0.1mum-gate InP HEMTs using i-line lithography. Higher throughput lithography processes were achieved by applying i-line lithography instead of electron beam (EB) lithography. The process we developed has three important technical aspects: shrinking the photoresist pattern, dry etching the multi-layer resists, and shrinking the PMMA resist. The controllability of gate lengths was good enough to realize circuit operation. Using our process, we fabricated a T-shaped 0.1mum-gate InP HEMT that showed a transconductance of 880 mS/mm and a cut-off frequency of 202 GHz. This performance equaled that of a device produced using EB lithography.

引用

页码：65 / 68

页数：4

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