Undetectable fault removal of sequential circuits based on unreachable states

被引：7
|
作者：
Yotsuyanagi, H [1 ]
Kinoshita, K [1 ]
机构：
[1] Osaka Univ, Fac Engn, Dept Appl Phys, Suita, Osaka 5600871, Japan
来源：
16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/VTEST.1998.670866
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable states and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.
引用
收藏
页码：176 / 181
页数：6
相关论文
共 50 条
  • [41] State relaxation based subsequence removal for fast static compaction in sequential circuits
    Hsiao, MS
    Chakradhar, ST
    DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS, 1998, : 577 - 582
  • [42] New techniques for untestable fault identification in sequential circuits
    Syal, Marian
    Hsiao, Michael S.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2006, 25 (06) : 1117 - 1131
  • [43] DESIGN OF A SEQUENTIAL TEST FOR A MULTIPLE FAULT IN ASYNCHRONOUS CIRCUITS
    PLITMAN, AD
    AUTOMATION AND REMOTE CONTROL, 1974, 35 (07) : 1123 - 1131
  • [44] Parallel sequence fault simulation for synchronous sequential circuits
    Kung, CP
    Lin, CS
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1996, 9 (03): : 267 - 277
  • [45] BART: A bridging fault test generator for sequential circuits
    Cusey, JP
    Patel, JH
    ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 838 - 847
  • [46] Serial diagnostic fault simulation for synchronous sequential circuits
    Chen, SC
    Jou, JM
    INTEGRATION-THE VLSI JOURNAL, 1997, 23 (02) : 157 - 170
  • [47] FAULT EFFECTS IN ASYNCHRONOUS SEQUENTIAL LOGIC-CIRCUITS
    SHIEH, MD
    WEY, CL
    FISHER, PD
    IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1993, 140 (06): : 327 - 332
  • [48] Dynamic fault diagnosis for sequential circuits on reconfigurable hardware
    Kocan, F
    Saab, DG
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 214 - 215
  • [49] REDUNDANCY AND FAULT-DETECTION IN SEQUENTIAL-CIRCUITS
    ABRAMOVICI, M
    BREUER, MA
    IEEE TRANSACTIONS ON COMPUTERS, 1979, 28 (11) : 864 - 865
  • [50] Parallel sequence fault simulation for synchronous sequential circuits
    Industrial Technology Research Inst, Hsinchu, Taiwan
    J Electron Test Theory Appl JETTA, 3 (267-277):
12345