Undetectable fault removal of sequential circuits based on unreachable states

被引：7
|
作者：
Yotsuyanagi, H [1 ]
Kinoshita, K [1 ]
机构：
[1] Osaka Univ, Fac Engn, Dept Appl Phys, Suita, Osaka 5600871, Japan
来源：
16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年
关键词：
D O I：
10.1109/VTEST.1998.670866
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable states and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.
引用
收藏
页码：176 / 181
页数：6
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