Heuristics to minimize multiple-valued decision diagrams

被引:0
|
作者
Babu, HMH [1 ]
Sasao, T [1 ]
机构
[1] Kyushu Inst Technol, Dept Comp Sci & Elect, Iizuka, Fukuoka 8208502, Japan
关键词
binary decision diagram (BDD); multiple-valued decision diagram (MDD); multiple-output function; multiple-walled logic; FPGA design;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we propose a method to minimize multiple-valued decision diagrams (MDDs) for multiple-output functions. We consider the following: (1) a heuristic for encoding the 2-valued inputs; and (2) a heuristic for ordering the multiple-valued input variables based on sampling where each sample is a group of outputs. We first generate a 4-valued input 2-valued multiple-output function from the given 2-valued input 2-valued functions. Then we construct an MDD for each sample and find a good variable ordering. Finally, we generate a variable ordering from the orderings of MDDs representing the samples and minimize the entire MDDs. Experimental results show that the proposed method is much faster, and for many benchmark functions, it produces MDDs with fewer nodes than sifting. Especially, the proposed method generates much smaller MDDs in a short time for benchmark functions when several 2-valued input variables are grouped to form multiple-valued variables.
引用
收藏
页码:2498 / 2504
页数:7
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