Sub-60mV-Swing Negative-Capacitance FinFET without Hysteresis

被引:0
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作者
Li, Kai-Shin [1 ]
Chen, Pin-Guang [2 ,3 ]
Lai, Tung-Yan [1 ]
Lin, Chang-Hsien [1 ]
Cheng, Cheng-Chih [3 ]
Chen, Chun-Chi [1 ]
Wei, Yun-Jie [1 ]
Hou, Yun-Fang [1 ]
Liao, Ming-Han [2 ]
Lee, Min-Hung [3 ]
Chen, Min-Cheng [1 ]
Sheih, Jia-Min [1 ]
Yeh, Wen-Kuan [1 ]
Yang, Fu-Liang [4 ]
Salahuddin, Sayeef [5 ]
Hu, Chenming [5 ]
机构
[1] Natl Appl Res Labs, Natl Nano Device Labs, Hsinchu, Taiwan
[2] Natl Taiwan Univ, Dept Mech Engn, Taipei, Taiwan
[3] Natl Taiwan Normal Univ, Inst Electroopt Sci & Technol, Taipei, Taiwan
[4] Acad Sinica, Res Ctr Appl Sci, Taipei, Taiwan
[5] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we report the first Negative-Capacitance FinFET. ALD Hf0.42Zr0.58O2 is added on top of the FinFET's gate stack. The test devices have a floating internal gate that can be electrically probed. Direct measurement found the small-signal voltage amplified by 1.6X maximum at the internal gate in agreement with the improvement of the subthreshold swing (from 87 to 55mV/decade). I-ON increased by >25% for the I-OFF. For the first time, we demonstrate that raising HfZrO2 ferroelectricity, by annealing at higher temperature, reduces and eliminates IV hysteresis and increases the voltage gain. These discoveries will guide future theoretical and experimental work.
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页数:4
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