Batch fabrication of through-wafer vias in CMOS wafers for 3-D packaging applications

A technique for fabrication of through-wafer vias in silicon wafers containing complementary metal-oxide-semiconductor (CMOS) circuitry is presented. The application of the presented through-wafer vias with existing wafer level chip size packaging (VVLCSP) technologies enables fabrication of very dense packages. The through-wafer vias are fabricated entirely by low temperature, CMOS compatible processes, thus designed to allow for post processing of vias in fully processed CMOS wafers. The fabrication of the presented through-wafer vias is based on KOH etching of wafer through-holes, low temperature deposition of dielectric material, and electrodeposition of photoresist and via metallization (Cu and Ni). A simple solution to the well-known CMOS compatibility issue of KOH is employed by protecting the front side of the CMOS wafer using a combination of plasma enhanced chemical vapor deposited (PECVD) silicon nitride, sputter deposited TiW/Au and electroplated Au. This protection scheme allows for batch processing of through-wafer vias. The fabricated through-wafer vias have a serial resistance of 40 mOmega and a parasitic capacitance to the Si substrate of 2.5 pF.