A programmable DSP architecture for wireless communication systems

被引：0

作者：

Kamalizad, A ^{[1
]}

Tabrizi, N ^{[1
]}

Bagherzadeh, N ^{[1
]}

Hatanaka, A ^{[1
]}

机构：

[1] Univ Calif Irvine, EECS Dept, Irvine, CA 92697 USA

来源：

16TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURE AND PROCESSORS, PROCEEDINGS | 2005年

关键词：

PARALLEL;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Programmable solutions for fast mobile communication systems are attracting ever-growing attention due to different and also evolving communication standards. They overcome the shortcomings of ASIC design, by allowing multimode operation, and general-purpose processors by exploiting, the inherent data level parallelism in the application. MaRS, a Macro-pipelined Reconfigurahle System, is a domain specific programmable parallel DSP architecture, aimed at harnessing the inherent parallelism.; in such applications. In this paper, we present them MaRS architecture along with the latest modifications and algorithms that are mapped onto it, We have mapped an IEEE 802.11a WLAN transmitter including a parallel FFT and soft decision Viterbi decoder on MaRS. Our simulation results show that the performance achieved on MaRS meets the stringent timing constraints of the IEEE 802.11a baseband transceiver at its highest rate, with 20% slack leaving a playground for system level power optimization. Finally we have mapped the EEMBC telecom suite on MaRS to evaluate and compare our architecture with existing architectures.

引用

页码：231 / 238

页数：8

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