Parallel Gate Operations Fidelity in a Linear Array of Flip-Flop Qubits

被引:6
|
作者
Rei, Davide [1 ]
Ferraro, Elena [1 ]
De Michielis, Marco [1 ]
机构
[1] CNR IMM Agrate Unit, Via C Olivetti 2, I-20864 Agrate Brianza, Monza E Brianza, Italy
关键词
1; f noise; donor qubit; flip-flop qubit; parallel quantum gate; qubit array; QUANTUM; SILICON; STORAGE; DONORS;
D O I
10.1002/qute.202100133
中图分类号
O4 [物理学];
学科分类号
0702 ;
摘要
Quantum computers based on silicon are promising candidates for long term universal quantum computation due to the long coherence times of electron and nuclear spin states. Furthermore, the continuous progress of micro- and nano-electronics, also related to the scaling of metal-oxide-semiconductor systems, makes it possible to control the displacement of single dopants thus suggesting their exploitation as qubit holders. Flip-flop qubit is a donor based qubit where interactions between qubits are achievable for distance up to several hundred nanometers. In this work, a linear array of flip-flop qubits is considered and the unwanted mutual qubit interactions due to the simultaneous application of two one-qubit and two two-qubit gates are included in the quantum gate simulations. In particular, by studying the parallel execution of couples of one-qubit gates, namely Rz(-pi 2)$R_z(-\frac{\pi }{2})$ and Rx(-pi 2)$R_x(-\frac{\pi }{2})$, and of couples of two-qubit gate, that is, iSWAP$\sqrt {\text{i}\text{SWAP}}$, a safe inter-qubit distance is found where unwanted qubit interactions are negligible thus leading to parallel gates fidelity up to 99.9%.
引用
收藏
页数:7
相关论文
共 50 条
  • [1] Impact of Parallel Gating on Gate Fidelities in Linear, Square, and Star Arrays of Noisy Flip-Flop Qubits
    De Michielis, Marco
    Ferraro, Elena
    [J]. ADVANCED QUANTUM TECHNOLOGIES, 2024,
  • [2] Parallel Gate Fidelity of Flip-Flop Qubits in Small 1D-and 2D-Arrays in a Noisy Environment
    De Michielis, Marco
    Rei, Davide
    Ferraro, Elena
    [J]. ADVANCED QUANTUM TECHNOLOGIES, 2024, 7 (06)
  • [3] OPERATING A LOGIC GATE AS A FLIP-FLOP
    WILKE, W
    [J]. ELECTRONICS, 1974, 47 (06): : 120 - 121
  • [4] Fast high-fidelity single-qubit gates for flip-flop qubits in silicon
    Calderon-Vargas, F. A.
    Barnes, Edwin
    Economou, Sophia E.
    [J]. PHYSICAL REVIEW B, 2022, 106 (16)
  • [5] Optical implementation of a parallel fuzzy flip-flop
    Zhang, SQ
    Karim, MA
    Chen, XW
    Alam, MF
    [J]. MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 1997, 16 (01) : 44 - 48
  • [6] A 1860kG CMOS gate array with GTL input flip-flop circuits
    Tomobe, K
    Takahashi, T
    Kawashima, M
    Sonobe, Y
    Kiyuna, T
    Yamamoto, S
    [J]. PROCEEDINGS OF THE IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1996, : 61 - 64
  • [7] A new flip-flop gate based on floating gates
    Sinencio, LFC
    Sanchez, AD
    Angulo, JR
    [J]. 2004 1st International Conference on Electrical and Electronics Engineering (ICEEE), 2004, : 219 - 221
  • [8] Simplified Flip-Flop Gate Model for EEMI Injection
    Valbuena, Luis
    Heileman, Gregory L.
    Hemmady, Sameer
    Schamiloglu, Edl
    [J]. PROCEEDINGS OF THE 2019 INTERNATIONAL CONFERENCE ON ELECTROMAGNETICS IN ADVANCED APPLICATIONS (ICEAA), 2019, : 845 - 850
  • [9] AN OPTICAL FLIP-FLOP SENSOR ARRAY WITH DIGITAL OUTPUTS
    WOUTERS, SE
    LIAN, W
    [J]. VLSI AND COMPUTER PERIPHERALS: VLSI AND MICROELECTRONIC APPLICATIONS IN INTELLIGENT PERIPHERALS AND THEIR INTERCONNECTION NETWORKS, 1989, : C96 - C98
  • [10] RESISTOR ARRAY DEBOUNCES D FLIP-FLOP MIXER
    WATTS, M
    [J]. EDN, 1990, 35 (08) : 184 - 184